In a wireless communications interface as may be used in Desktop Area Networks, where communication is desired with a computer or a peripheral device, between computers, or between a computer and a peripheral device located in an office or between adjacent offices, broadband transceivers are needed to achieve high data transmission rates. As such wireless communications interfaces are battery powered for maximum transportability, it is desirable to prolong the life of the battery to ensure a reasonable duration of use. This may be accomplished through reduced power consumption.
It further is commercially desirable to avoid the necessity of obtaining a license from the Federal Communication Commission (FCC) in order to operate a wireless communications interface. One way to achieve this goal is to design the transceiver to operate within exempted frequency bands without exceeding the power limits designated by the FCC. The exempted frequency bands include the Industrial, Scientific and Medical (ISM) frequency bands nominally at 27 MHz, 900 MHz, 2.4 GHz, and 5.7 GHz.
A still further constraint on the design of a transceiver for wireless communications interfaces is manufacturing cost. It is a well known historical fact that the lower the frequency of operation, the lower the cost of the hardware comprising the transceiver.
Prior systems attempting to satisfy the above constraints have failed because they have not been able to achieve in combination both an acceptable level of frequency stability in a reasonably short time, and a broad enough bandwidth to achieve desired data rates without exceeding FCC power limits within the exempted frequency bands described above. One reason for such failure is the use of either programmable phase lock loops or phase lock loops that require frequency dividers as described in U.S. Pat. Nos. 4,052,672; 4,602,225; 4,679,005; 5,027,429; 5,079,526; and 5, 374,903. Dividers consume excessive amounts of power. Another reason for such failure is that even when a phase lock loop without dividers as described in U.S. Pat. No. 4,118,673 is used, there has been an inability to achieve either a phase lock that is fast enough to avoid data degredation at the 900 MHz data rates of the present invention, or an extension of transceiver bandwidth down to DC for FSK modulated carrier signals.
While DC frequency modulation as described in U.S. Pat. Nos. 4,602,225 and 5,079,526 has been achieved, upper frequency limitations have prevented the bandwidths necessary for desired data rates of the order of 100 Kilobits per second and higher.
In accordance with the invention, a transceiver is provided with an offset phase locked loop which has no power consuming frequency dividers, and which is sweeped into a fast lock by varying bias levels in transistors that comprise a phase detecting component of the loop. In addition, components within the phase lock loop which have functionalities that are required for both transmitting and receiving are shared to avoid unnecessary power consumption. Further, a feed forward compensation method is used to achieve bandwidths from DC to above 10 MHz, and to provide additional aid in achieving a fast phase lock.